Commercialization of a Low Cost Wafer Bumping Process for Flip Chip Applications

Andrew J.G. Strandjord, Scott F. Popelar, and Curt A. Erickson
IC Interconnect
1025 Elkton Drive
Colorado Springs, CO
Phone: 719-533-1030
Fax: 719-533-1021
ici@icinterconnect.com
www.icinterconnect.com

The application of flip chip technology provides many advantages over conventional integrated circuit packaging techniques (i.e. wire bonding) in terms of cost, electrical performance, I/O density, package size, and reliability. However, widespread use of flip chip as a surface mount alternative has been slow to develop due to the multi-million dollar investment in capital equipment required to bump wafers using traditional bumping techniques (i.e. vapor deposition, photolithography, electroplating, etc.). To lower this barrier to commercialization, two lower cost wafer bumping techniques have been brought together and implemented into a high volume contract wafer bumping facility (IC Interconnect). This process combines some of the newly developed electroless nickel/gold deposition techniques (batch wet chemistry) with conventional stencil based solder printing technology. This paper describes the above wafer bumping process and some of the realities associated with taking these technologies from a laboratory environment into high volume production.

For the complete document, please contact Hank Carey at hcarey@icinterconnect.com or 719-533-1030 ext121